The present invention relates to a computer-implemented method for an automatic synthesis of distributed embedded systems, wherein the tasks to be processed by the system are mapped to a hardware structure having a plurality of processing units such that predefined time limits of the tasks are met.
Methods for an automatic synthesis of distributed embedded systems have long been researched. F. Slomka: Mehrkriterienoptimierung verteilter Echtzeitsysteme mit Tabu-Search, doctoral thesis, engineering department of the university of Erlangen-Nuremberg, Fortschritt-Bericht VDI, series 20, no. 353, VDI-Verlag, Dusseldorf, 2002, gives an overview over this research. It is the object of such a system synthesis to map individual tasks to be processed by the system to a hardware architecture. Thus, it has to be decided which tasks have to be implemented by which processor. It is the object of the synthesis to have the given amount of tasks processed by a minimal hardware structure. Most of the time, the tasks have to meet predetermined time limits, which may also be specified by a series of tasks. It must be possible to implement the hardware architecture, including the infrastructure for the software tasks, the operating system, in view of this boundary condition and any further boundary conditions to be specified, such as energy consumption, electrical power consumption and operating temperature at minimal costs, which is mostly expressed by the chip area. For most jobs, the tasks are assigned to the processors by exact or heuristic optimisation methods, whereupon it is checked whether the specified boundary conditions are met. The assignment of the tasks to the processors is systematically changed by the optimisation method until a sufficiently minimal hardware architecture is found or the search may be terminated.
Car manufacturers (OEM) model the different tasks in the field of electricity and electronics as functional diagrams. A functional diagram consists of blocks, wherein each block determines a specific function. Each block may realise a task. The data inputs and outputs of the blocks are interconnected, which shows the data flow between the blocks. For functional correctness, it is important that the blocks are chronologically processed and the stipulated time limits are met. In a first step, the car manufacturer distributes the blocks to control devices without having detailed knowledge of the system architecture (such as number and type of CPUs and peripheral devices, memory size) of the control device, in particular the software architecture (such as scheduling methods, process number, interrupt service routines (ISR), ISR/process priorities). On account of the complexity and the historical restrictions to the block distribution to control devices, this optimisation often yields suboptimal solutions. The time limits are not sufficiently taken into account. In a second step, it is the object of the supplier of a control device to devise a system architecture of the control device which particularly meets the stipulated time limits. If the distribution in the first step is incorrectly selected: first, the real-time criteria of a control device cannot be satisfied. Second, the development of the necessary optimisation measures for achieving real-time capability is quite complex. Third, a hardware oversizing is necessary in view of an optimal solution in the first step. The first item might lead to product recalls and thus to a loss of prestige, whereas the second and third items increase the costs.